A quantum-inspired processor, also known as a quantum-inspired computer or quantum-classical hybrid computer, is a type of computing system that incorporates certain aspects of quantum computing while still operating within the realm of classical computing.
Have you ever had to choose the best option from a plethora of alternatives, such as choosing the shortest route to a specific location while taking traffic and travel time into account? If so, the problem you were dealing with is what is formally known as a “combinatorial optimization problem.”
Although they are mathematically described, these issues arise in a variety of real-world settings, including logistics, network routing, machine learning, and materials science.
However, solving large-scale combinatorial optimization problems with conventional computers requires a significant amount of computational power, which forces researchers to use alternative strategies. The “Ising model,” which uses mathematics to depict the magnetic orientation of atoms, or “spins,” in a ferromagnetic material, is one such strategy.
At high temperatures, these atomic spins are oriented randomly. The spins align, however, to attain the minimal energy state where each spin’s orientation is dependent on its neighbors, as the temperature drops. It turns out that this ‘annealing’ procedure can be used to simulate combinatorial optimization issues in a way that the final state of the spins produces the best result.
Quantum-inspired processors typically utilize quantum-inspired algorithms and techniques, such as quantum annealing or quantum-inspired optimization algorithms, to solve complex problems more efficiently than classical computers. These algorithms take inspiration from quantum computing principles but are implemented using classical hardware.
The advantage of our approach is that the amount of data transmitted between the chips is extremely small. Although its principle is simple, this method allows us to realize a scalable, fully connected LSI system for solving combinatorial optimization problems through simulated annealing.
Professor Takayuki Kawahara
Researchers have sought to construct semiconductor devices employing large-scale integration (LSI) technology in an effort to replicate the behavior of spins via annealing processors that use quantum devices.
In particular, Professor Takayuki Kawahara’s research group at Tokyo University of Science (TUS) in Japan has been making important breakthroughs in this particular field.
In 2020, Prof. Kawahara and his colleagues presented at the 2020 international conference, IEEE SAMI 2020, one of the first fully coupled (that is, accounting for all possible spin-spin interactions instead of interactions with only neighboring spins) LSI annealing processors, comprising 512 fully-connected spins.
Their work appeared in the journal IEEE Transactions on Circuits and Systems I: Regular Papers. These systems are notoriously hard to implement and upscale owing to the sheer number of connections between spins that needs to be considered.
A potential solution to the scalability issue was to run several fully connected chips in parallel, however this required an unreasonably high number of interconnections (wires) between chips.
In a recent study published in Microprocessors and Microsystems, Prof. Kawahara and his colleague demonstrated a clever solution to this problem. They created a novel technique where the energy state calculation of the system is initially split among numerous completely connected processors, establishing a ‘array calculator.’
The findings from the remaining chips are then combined and computed by a second type of chip known as a ‘control chip,’ which is used to update the values of the simulated spins.
“The advantage of our approach is that the amount of data transmitted between the chips is extremely small,” explains Prof. Kawahara. “Although its principle is simple, this method allows us to realize a scalable, fully connected LSI system for solving combinatorial optimization problems through simulated annealing.”
Using widely used programmable semiconductor devices known as commercial FPGA chips, the researchers successfully put their strategy into practice. They created a fully linked annealing system with 384 spins and utilized it to address a number of optimization issues, such as the 384-node maximum cut problem and the 92-node graph coloring challenge.
Most importantly, these proof-of-concept tests demonstrated that the suggested strategy actually improves performance. When solving the maximum cut issue, the FPGA implementation was 584 quicker and 46 times more energy efficient than a typical current CPU simulating the same annealing system.
Now, with this successful demonstration of the operating principle of their method in FPGA, the researchers plan to take it to the next level.
“We wish to produce a custom-designed LSI chip to increase the capacity and greatly improve the performance and power efficiency of our method,” Prof. Kawahara remarks. “This will enable us to realize the performance required in the fields of material development and drug discovery, which involve very complex optimization problems.”
Prof. Kawahara concludes by saying that he wants to encourage the application of their findings to resolve actual societal issues. His team aspires to perform collaborative research with businesses and apply their methodology to the fundamentals of semiconductor design technology, clearing the way for the resurgence of semiconductors in Japan.
