Denser, more potent computer chips are needed for emerging AI applications like chatbots that produce natural human language. However, since bulk materials, which are boxy 3D structures used to manufacture semiconductor chips, it is exceedingly challenging to stack many layers of transistors to produce denser integrations.
However, it is possible to build more potent devices by stacking semiconductor transistors constructed from ultrathin 2D materials, which are each only around three atoms thick. To this end, MIT researchers have now demonstrated a novel technology that can effectively and efficiently “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip to enable denser integrations.
It has been extremely difficult to grow 2D materials directly onto a silicon CMOS wafer because the procedure typically calls for temperatures of about 600 degrees Celsius, while silicon transistors and circuits could malfunction at temperatures higher than 400 degrees.
The multidisciplinary MIT research team has now created a low-temperature growing method that doesn’t harm the chip. The process enables the direct integration of 2D semiconductor transistors on top of conventional silicon circuitry.
In the past, scientists have produced 2D materials off-chip or off-wafer, then moved them there. This frequently results in flaws that reduce the effectiveness of the finished devices and circuits.
Also, transferring the material smoothly becomes extremely difficult at wafer-scale. By contrast, this new process grows a smooth, highly uniform layer across an entire 8-inch wafer.
The time needed to grow these materials can also be reduced considerably thanks to the new technique. The new method can build a homogenous layer of TMD material over complete 8-inch wafers in less than an hour, when earlier efforts needed more than a day to do so.
The researchers were able to successfully integrate a 2D material layer onto far bigger surfaces than had previously been proven because to the new technology’s quick speed and great uniformity. Because 8-inch or larger wafers are essential for certain applications, their approach is better suited for usage in them.
“Using 2D materials is a powerful way to increase the density of an integrated circuit. What we are doing is like constructing a multistory building. If you have only one floor, which is the conventional case, it won’t hold many people. But with more floors, the building will hold more people that can enable amazing new things. Thanks to the heterogenous integration we are working on, we have silicon as the first floor and then we can have many floors of 2D materials directly integrated on top,” says Jiadi Zhu, an electrical engineering and computer science graduate student and co-lead author of a paper on this new technique.
Zhu wrote the paper with co-lead-author Ji-Hoon Park, an MIT postdoc; corresponding authors Jing Kong, professor of electrical engineering and computer science (EECS) and a member of the Research Laboratory for Electronics; and Tomás Palacios, professor of EECS and director of the Microsystems Technology Laboratories (MTL); as well as others at MIT, MIT Lincoln Laboratory, Oak Ridge National Laboratory, and Ericsson Research. The paper appears today in Nature Nanotechnology.
Using 2D materials is a powerful way to increase the density of an integrated circuit. What we are doing is like constructing a multistory building. If you have only one floor, which is the conventional case, it won’t hold many people. But with more floors, the building will hold more people that can enable amazing new things. Thanks to the heterogenous integration we are working on, we have silicon as the first floor and then we can have many floors of 2D materials directly integrated on top.
Jiadi Zhu
Slim materials with vast potential
Molybdenum disulfide, the 2D material that the researchers concentrated on, is transparent, flexible, and possesses strong electrical and optical properties that make it the perfect material for a semiconductor transistor. It is composed of a one-atom layer of molybdenum sandwiched between two atoms of sulfide.
Growing thin films of molybdenum disulfide on a surface with good uniformity is often accomplished through a process known as metal-organic chemical vapor deposition (MOCVD).
Two molybdenum and sulfur-containing organic chemical compounds, molybdenum hexacarbonyl and diethylene sulfur, evaporate and heat up inside the reaction chamber, where they “decompose” into smaller molecules. Then they link up through chemical reactions to form chains of molybdenum disulfide on a surface.
However, the precursor molybdenum and sulfur compounds must be decomposed at temperatures greater than 550 degrees Celsius in order for silicon circuits to begin to deteriorate.
To begin with, the researchers used their creative thinking to build and construct a whole new furnace for the metal-organic chemical vapor deposition method.
The oven has two chambers: a front low-temperature area where the silicon wafer is inserted and a back high-temperature area. Vaporized molybdenum and sulfur precursors are pumped into the furnace.
The temperature is kept below 400 degrees Celsius in the low-temperature area, where the molybdenum remains, just hot enough to disintegrate the molybdenum precursor but not hot enough to harm the silicon chip.
The sulfur precursor passes through and breaks down at the high-temperature area. The chemical reaction to generate molybdenum disulfide on the surface of the wafer then flows back into the low-temperature area.
“You can think about decomposition like making black pepper you have a whole peppercorn and you grind it into a powder form. So, we smash and grind the pepper in the high-temperature region, then the powder flows back into the low-temperature region,” Zhu explains.
Faster growth and better uniformity
The fact that silicon circuits frequently contain copper or aluminum as the top layer so the chip can be linked to a package or carrier before it is put onto a printed circuit board is a drawback of this method. However, sulfur makes these metals sulfurize, which reduces their conductivity just as some metals rust when exposed to air.
The researchers prevented sulfurization by first depositing a very thin layer of passivation material on top of the chip. Then later they could open the passivation layer to make connections.
Additionally, they inserted the silicon wafer vertically, as opposed to horizontally, into the low-temperature area of the furnace. Because it is positioned vertically, neither end is too close to the area of high temperature, protecting the wafer from heat damage.
Additionally, rather than flowing along a horizontal surface as they collide with the vertical chip, the molybdenum and sulfur gas molecules spin as they hit the chip. The growth of molybdenum disulfide is enhanced by this circulation action, which also increases material homogeneity.
In addition to yielding a more uniform layer, their method was also much faster than other MOCVD processes. They could grow a layer in less than an hour, while typically the MOCVD growth process takes at least an entire day.
Using the state-of-the-art MIT.Nano facilities, they were able to demonstrate high material uniformity and quality across an 8-inch silicon wafer, which is especially important for industrial applications where bigger wafers are needed.
“By shortening the growth time, the process is much more efficient and could be more easily integrated into industrial fabrications. Plus, this is a silicon-compatible low-temperature process, which can be useful to push 2D materials further into the semiconductor industry,” Zhu says.
The researchers intend to improve this method in the future and apply it to the growth of numerous stacked layers of 2D transistors. Additionally, they aim to investigate how flexible surfaces like polymers, fabrics, and even papers can be grown using a low temperature technique. This would make it possible to incorporate semiconductors into commonplace items like clothing and notebooks.
This work is partially funded by the MIT Institute for Soldier Nanotechnologies, the National Science Foundation Center for Integrated Quantum Materials, Ericsson, MITRE, the U.S. Army Research Office, and the U.S. Department of Energy. The project also benefitted from the support of TSMC University Shuttle.
